This invention relates generally to semiconductor integrated circuits and specifically to protecting the gate inputs of metal-insulator-semiconductor (MIS) transistors with a protective resistor connected to ground or a power supply rail, and in particular, to methods of fabricating high resistance value protective resistors when using a self-aligning silicide process.
FIG. 1 illustrates a prior art complementary insulated gate field effect MIS transistor integrated circuit (IC) 10 which is fabricated with a self-aligning silicide process. IC 10 has a p-type well 12 formed on the main surface of an n-type semiconductor substrate 14, a pair of polycide structure gate electrodes 16 and 18, a p-type source/drain region 20 and an n-type source/drain region 22. Region 20 and region 22 are self-aligned by masking the gate electrode 16 and the gate electrode 18. A pair of first type "channel stoppers" 24, which are heavily doped with p-type impurities, are formed in well 12, and are used to prevent MOS parasitics. A pair of second type channel stoppers 26, which are heavily doped with n-type impurities, are formed on substrate 14, and are used to prevent latch-up. Gate electrodes 16 and 18 each comprise a polycrystalline silicon film and a film of a refractory (high melting-point) metal disilicide, such as TiSi.sub.2 (titanium disilicide), and are formed on substrate 14 and well 12 over gate insulation films. An n-channel MOS transistor 28 is formed by the gate electrode 18 and region 22 on well 12. A p-channel MOS transistor 30 is formed by the gate electrode 16 and region 20 on substrate 14. A self-aligned silicide process is used to reduce the gate resistance, the contact resistance, and the diffusion resistance. The process overlays regions 20 and 22, and channel stoppers 24 and 26, with titanium or some other refractory metal. A heat treatment is then used to alloy the refractory metal to form a metal disilicide layer.
Input impedances at the gates of MIS transistors 28 and 30 are extremely high in IC 10, due to the insulated gate construction. Unlike a bipolar transistor input, static electric charges are not readily bled off in MIS transistors without some protection means being added. Input clamping diodes are often used to prevent static and power supply glitches from destroying the input of IC 10. Without these precautions, the breakdown voltage of the gate insulation layer can easily be exceeded (thus destroying the device). Diodes are commonly used between each input and both supply rails (V.sub.DD and V.sub.SS) for the clamping. Alternatively, pull-down or pull-up resistors are used on inputs to bleed-off excessive electrical charges. Transistor 30 has a pull-up resistor 32 that is connected to gate electrode 16 through an aluminum wire 34 and a contact hole 36. Resistor 32 comprises a diffusion region in a part of channel stopper 26 and is connected to V.sub.DD through an aluminum wire 40 and a contact hole 42. Transistor 28 has a pull-down resistor 44 that is connected to gate electrode 18 through an aluminum wire 46 and a contact hole 48. Resistor 44 comprises a diffusion region in a part of channel stopper 24 and is connected to V.sub.SS through an aluminum wire 50 and a contact hole 52.
FIG. 2 illustrates that channel stoppers 24 and 26 have a surface refractory metal disilicide film 54. The diffusion regions comprising resistors 32 and 44 are therefore heavily doped with impurities (similar to the concentration used in the source/drain regions) and, as such, have low bulk resistance values. This runs contrary to the goal of obtaining the higher resistance values that are preferable for pull-up and pull-down resistors (e.g., resistors 32 and 44). But limiting the high end of permissible resistor values is risk that is taken of experiencing a voltage that can break down the gate insulator film. Since the gate breakdown voltages in self-aligned silicide process gate electrodes are extremely low, the value of the resistance for resistors 32 and 44 must be set to a compromise value. Resistors 32 and 44 can be increased in value by increasing the length of the diffusion resistance region (e.g., increasing the distances between the contact holes 36 and 42, and between contact holes 42 and 48). Although this will increase the value of resistors 32 and 44, it runs counter to the very desirable aim of keeping finer features which results in much higher IC 10 packing densities.
An object of the present invention is to have a relatively large resistance value pull-up or pull-down resistor in a very small space, even when a channel stopper or other low-resistivity diffusion region formed by a self-aligned silicide process is used.